//QxSourse information February 22, 2004				

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`define TEST 1 //To include test



`ifdef TEST
//module CounterTest ( Reset, Clk, Count, Equ   );
module CounterTest ( Reset, Clk, Count, Equ   );

   input  Reset, Clk;
   output [7:0]Count;
   output Equ;


   wire [7:0]Count;
   wire Equ;

   assign Equ = (Count == 8'h0);

   Counter Counter1( .Reset(Reset), .Clk(Clk), .Count(Count) );
endmodule
`endif

//=========================================
//module Counter ( Reset, Clk, Count)
module Counter ( Reset, Clk, Count);
  input  Reset, Clk;
  output Count;

  reg [7:0]Count; //Register used for counter

  always@(posedge Clk)
  begin
    if (!Reset) 
       Count <= 8'h0; //8 bits of 0
     else 
       Count <= Count + 1;
  end
endmodule